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?2009 silicon storage technology, inc. s71342-01-000 11/09 1 the sst logo and superflash are registered trademarks of silicon storage technology, inc. csf is a trademark of silicon storage technology, inc. these specifications are subject to change without notice. data sheet 16 mbit (x8/x16) concurrent superflash sst36vf1601g / sst36vf1602g features: ? organized as 1m x16 or 2m x8 ? dual bank architecture for concurrent read/write operation ? 16 mbit bottom sector protection - sst36vf1601g: 4 mbit + 12 mbit ? 16 mbit top sector protection - sst36vf1602g: 12 mbit + 4 mbit ? single 2.7-3.6v for read and write operations ? superior reliability ? endurance: 100,000 cycles (typical) ? greater than 100 years data retention ? low power consumption: ? active current: 6 ma typical ? standby current: 4 a typical ? auto low power mode: 4 a typical ? hardware sector protection/wp# input pin ? protects the 4 outermost sectors (8 kword) in the smaller bank by driving wp# low and unprotects by driving wp# high ? hardware reset pin (rst#) ? resets the internal state machine to reading array data ? byte# pin ? selects 8-bit or 16-bit mode ? sector-erase capability ? uniform 2 kword sectors ? chip-erase capability ? block-erase capability ? uniform 32 kword blocks ? erase-suspend / erase-resume capabilities ? security id feature ? sst: 128 bits ? user: 256 byte ? fast read access time ? 70 ns ? latched address and data ? fast erase and program (typical): ? sector-erase time: 18 ms ? block-erase time: 18 ms ? chip-erase time: 35 ms ? program time: 7 s ? automatic write timing ? internal v pp generation ? end-of-write detection ? toggle bit ? data# polling ? ready/busy# pin ? cmos i/o compatibility ? conforms to common flash memory interface (cfi) ? jedec standards ? flash eeprom pinouts and command sets ? packages available ? 48-ball tfbga (6mm x 8mm) ? 48-lead tsop (12mm x 20mm) ? 56-ball lfbga (8mm x 10mm) ? all non-pb (lead-free) devices are rohs compliant product description the sst36vf1601g and sst36vf1602g are 1m x16 or 2m x8 cmos concurrent read/write flash memory man- ufactured with sst proprietary, high performance cmos superflash memory technology. the split-gate cell design and thick oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. the devices write (program or erase) with a 2.7-3.6v power supply and conform to jedec standard pinouts for x8/x16 memories. featuring high performance program, the sst36vf160xg provide a typical program time of 7 sec and use toggle bit, data# polling, or ry/by# to detect the completion of the program or erase operation. to protect against inad- vertent write, the devices have on-chip hardware and soft- ware data protection schemes. designed, manufactured, and tested for a wide spectrum of applications, these devices are offered with a guaranteed endurance of 10,000 cycles. data retention is rated at greater than 100 years. these devices are suited for applications that require con- venient and economical updating of program, configura- tion, or data memory. for all system applications, the sst36vf160xg significantly improve performance and reliability, while lowering power consumption. these devices inherently use less energy during erase and pro- gram than alternative flash technologies, because the total energy consumed is a function of the applied voltage, cur- rent, and time of application. for any given voltage range, the superflash technology uses less current to program and has a shorter erase time; therefore, the total energy consumed during any erase or program operation is less than alternative flash technologies. sst36vf1601e / 1602e16mb (x8/x16) concurrent superflash
2 data sheet 16 mbit concurrent superflash sst36vf1601g / sst36vf1602g ?2009 silicon storage technology, inc. s71342-01-000 11/09 superflash technology provides fixed erase and program times, independent of the number of erase/program cycles that have occurred. therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose erase and program times increase with accumulated erase/program cycles. to meet high-density, surface-mount requirements, the sst36vf1601g and sst36vf1602g devices are offered in 48-ball tfbga, 48-lead tsop, and 56-ball lfbga packages. see figures 6, 7, and 8 for pin assignments. device operation memory operation functions are initiated using standard microprocessor write sequences. a command is written by asserting we# low while keeping ce# low. the address bus is latched on the falling edge of we# or ce#, which- ever occurs last. the data bus is latched on the rising edge of we# or ce#, whichever occurs first. auto low power mode these devices also have the auto lower power mode which puts them in a near-standby mode within 500 ns after data has been accessed with a valid read operation. this reduces the typical i dd active read current to 4 a. while ce# is low, the devices exit auto low power mode with any address transition or control signal transition used to initiate another read cycle, with no access time penalty. concurrent read/write operation the dual bank architecture of these devices allows the concurrent read/write operation whereby the user can read from one bank while programming or erasing in the other bank. for example, reading system code in one bank while updating data in the other bank. see table 1 below for more information. note: for the purposes of this table, write means to perform block- or sector-erase or program operations as applicable to the appropriate bank. the read operation of the sst36vf160xg is controlled by ce# and oe#, both of which have to be low for the system to obtain data from the outputs. ce# is used for device selection. when ce# is high, the chip is deselected and only standby power is consumed. oe# is the output control and is used to gate data from the output pins. the data bus is in a high impedance state when either ce# or oe# is high. refer to figure 9, the read cycle timing dia- gram, for further details. program operation these devices are programmed on a word-by-word or byte-by-byte basis depending on the state of the byte# pin. before programming, ensure that the sector which is being programmed is fully erased. the program operation is accomplished in three steps: 1. initiate software data protection using the three- byte load sequence. 2. load address and data. during the program operation, the addresses are latched on the falling edge of either ce# or we#, whichever occurs last. the data is latched on the rising edge of either ce# or we#, whichever occurs first. 3. initiate the internal program operation after the rising edge of the fourth we# or ce#, whichever occurs first. the program operation, once initi- ated, will be completed typically within 7 s. see figures 10 and 11 for we# and ce# controlled pro- gram operation timing diagrams and figure 25 for flow- charts. during the program operation, the only valid reads are data# polling and toggle bit. during the internal pro- gram operation, the host is free to perform additional tasks. any commands issued during an internal program opera- tion are ignored. table 1: concurrent read/write state bank 1 bank 2 read no operation read write write read write no operation no operation read no operation write
data sheet 16 mbit concurrent superflash sst36vf1601g / sst36vf1602g 3 ?2009 silicon storage technology, inc. s71342-01-000 11/09 sector-erase/blo ck-erase operation the sector- or block- erase operation allows the system to erase the device on a sector-by-sector (or block-by-block) basis. the sst36vf160xg offer both sector-erase and block-erase operations. the sector architecture is based on a uniform sector size of 2 kword. the sector-erase operation is initiated by execut- ing a six-byte command sequence with a sector-erase command (50h) and sector address (sa) in the last bus cycle. the block-erase mode is based on a uniform block size of 32 kword. block-erase is initiated by executing a six-byte command sequence with block-erase command (30h) and block address (ba) in the last bus cycle. the sector or block address is latched on the falling edge of the sixth we# pulse, while the command (50h or 30h) is latched on the rising edge of the sixth we# pulse. the internal erase oper- ation begins after the sixth we# pulse. any commands issued during the sector- or block-erase operation are ignored except erase-suspend and erase- resume. see figures 15 and 16 for timing waveforms. chip-erase operation the sst36vf1601g and sst36vf1602g provide a chip-erase operation, which erases the entire memory array to the ?1? state. this operation is useful when the entire device must be quickly erased. the chip-erase operation is initiated by executing a six- byte command sequence with chip-erase command (10h) at address 555h in the last byte sequence. the erase operation begins with the rising edge of the sixth we# or ce#, whichever occurs first. during the erase operation, the only valid read is toggle bit or data# polling. any com- mands issued during the chip-erase operation are ignored. see table 6 for the command sequence, figure 14 for timing diagram, and figure 29 for the flowchart. when wp# is low, any attempt to chip-erase will be ignored. erase-suspend/erase-r esume operations the erase-suspend operation temporarily suspends a sector- or block-erase operation thus allowing data to be read or programmed into any sector or block that is not engaged in an erase operation. the operation is executed by issuing a one-byte command sequence with erase-sus- pend command (b0h). the device automatically enters read mode no more than 10 s after the erase-suspend command had been issued. (t es maximum latency equals 10 s.) valid data can be read from any sector or block that is not suspended from an erase operation. reading at address location within erase-suspended sectors/blocks will output dq 2 toggling and dq 6 at ?1?. while in erase-sus- pend mode, a program operation is allowed except for the sector or block selected for erase-suspend. to resume a suspended sector-erase or block-erase operation, the system must issue an erase-resume com- mand. the operation is executed by issuing a one-byte command sequence with erase resume command (30h) at any address in the one-byte sequence. write operation status detection to optimize the system write cycle time, the sst36vf160xg provide two software means to detect the completion of a write (program or erase) cycle the soft- ware detection includes two status bits: data# polling (dq 7 ) and toggle bit (dq 6 ). the end-of-write detection mode is enabled after the rising edge of we#, which ini- tiates the internal program or erase operation. the actual completion of the nonvolatile write is asyn- chronous with the system. t herefore, data# polling or toggle bit maybe be read concurrent with the completion of the write cycle. if this occurs, the system may possibly get an incorrect result from the status detection process. for example, valid data may appear to conflict with either dq 7 or dq 6 . to prevent false results, upon detection of failures, the software routine should loop to read the accessed location an additional two times. if both reads are valid, then the device ha s completed the write cycle, otherwise the failure is valid.
4 data sheet 16 mbit concurrent superflash sst36vf1601g / sst36vf1602g ?2009 silicon storage technology, inc. s71342-01-000 11/09 ready/busy# (ry/by#) the sst36vf160xg include a ready/busy# (ry/by#) output signal. ry/by# is an open drain output pin that indi- cates whether an erase or program operation is in progress. since ry/by# is an open drain output, it allows several devices to be tied in parallel to v dd via an external pull-up resistor. after the rising edge of the final we# pulse in the command sequence, the ry/by# status is valid. when ry/by# is actively pulled low, it indicates that an erase or program operation is in progress. when ry/by# is high (ready), the devices may be read or left in standby mode. byte/word (byte#) the device includes a byte# pin to control whether the device data i/o pins operate x8 or x16. if the byte# pin is at logic ?1? (v ih ) the device is in x16 data configuration: all data i/0 pins dq 0 -dq 15 are active and controlled by ce# and oe#. if the byte# pin is at logic ?0?, the device is in x8 data con- figuration -- only data i/o pins dq 0 -dq 7 are active and con- trolled by ce# and oe#. the remaining data pins dq 8 - dq 14 are at hi-z, while pin dq 15 is used as the address input a -1 for the least significant bit of the address bus. data# polling (dq 7 ) when the sst36vf160xg are in an internal program operation, any attempt to read dq 7 will produce the com- plement of true data. once the program operation is com- pleted, dq 7 will produce valid data. during internal erase operation, any attempt to read dq 7 will produce a ?0?. once the internal erase operation is com- pleted, dq 7 will produce a ?1?. the data# polling is valid after the rising edge of fourth we# (or ce#) pulse for pro- gram operation. for sector-, block-, or chip-erase, the data# polling is valid after the rising edge of sixth we# (or ce#) pulse. see figure 12 for data# polling (dq 7 ) timing diagram and figure 26 for a flowchart. toggle bits (dq 6 and dq 2 ) during the internal program or erase operation, any con- secutive attempts to read dq 6 will produce alternating ?1?s and ?0?s, i.e., toggling between ?1? and ?0?. when the internal program or erase operation is completed, the dq 6 bit will stop toggling, and the device is then ready for the next operation. for sector-, block-, or chip-erase, the toggle bit (dq 6 ) is valid after the rising edge of sixth we# (or ce#) pulse. dq 6 will be set to ?1? if a r ead operation is attempted on an erase-suspended sector or block. if program oper- ation is initiated in a sector/block not selected in erase-sus- pend mode, dq 6 will toggle. an additional toggle bit is available on dq 2 , which can be used in conjunction with dq 6 to check whether a particular sector or block is being actively erased or erase-sus- pended. table 2 shows detailed bit status information. the to g g l e b i t ( d q 2 ) is valid after the rising edge of the last we# (or ce#) pulse of write operation. see figure 13 for toggle bit timing diagram and figure 26 for a flowchart. note: dq 7, dq 6, and dq 2 require a valid address when reading status information. the address must be in the bank where the operation is in progress in order to read the operation sta- tus. if the address is pointing to a different bank (not busy), the device will output array data. table 2: write operation status status dq 7 dq 6 dq 2 ry/by# normal operation standard program dq7# toggle no toggle 0 standard erase 0 toggle toggle 0 erase- suspend mode read from erase suspended sector/block 1 1 toggle 1 read from non-erase suspended sector/block data data data 1 program dq7# toggle n/a 0 t2.1 1342
data sheet 16 mbit concurrent superflash sst36vf1601g / sst36vf1602g 5 ?2009 silicon storage technology, inc. s71342-01-000 11/09 data protection the sst36vf160xg provide both hardware and software features to protect nonvolatile data from inadvertent writes. hardware data protection noise/glitch protection: a we# or ce# pulse of less than 5 ns will not initiate a write cycle. v dd power up/down detection: the write operation is inhibited when v dd is less than 1.5v. write inhibit mode: forcing oe# low, ce# high, or we# high will inhibit t he write operation. th is prevents inadvert- ent writes during power-up or power-down. hardware block protection the sst36vf1601g and sst36vf1602g provide hard- ware block protection which protects the outermost 8 kword in the smaller bank. the block is protected when wp# is held low. see figures 2, 3, 4, and 5 for block-pro- tection location. block protection is disabled by driving wp# high. this allows data to be erased or programmed into the protected sectors. wp# must be held high prior to issuing the write command and remain stable until after the entire write operation has completed. if wp# is left floating, it is inter- nally held high via a pull-up resistor, and the boot block is unprotected, enabling program and erase operations on that block. hardware reset (rst#) the rst# pin provides a hardware method of resetting the devices to read array data. when the rst# pin is held low for at least t rp, any in-progress operat ion will terminate and return to read mode (see). when no internal program/ erase operation is in progress, a minimum period of t rhr is required after rst# is driven high before a valid read can take place. see figures 22 and 21 for more informa- tion. the interrupted erase or program operation must be re-ini- tiated after the device resumes normal operation mode to ensure data integrity. software data protection (sdp) the sst36vf160xg devices implement the jedec approved software data protection (sdp) scheme for all data alteration operations, such as program and erase. these devices are shipped with the software data protec- tion permanently enabled. see table 6 for the specific soft- ware command codes. all program operations require the inclusion of the three- byte sequence. the three-byte load sequence is used to initiate the program operation, providing optimal protection from inadvertent write operations. sdp for erase opera- tions is similar to program, but a six-byte load sequence is required for erase operations. during sdp command sequence, invalid commands will abort the device to read mode within t rc. the contents of dq 15 -dq 8 can be v il or v ih , but no other value, during any sdp command sequence. common flash memory interface (cfi) these devices contain common flash memory interface (cfi) information that describes the characteristics of the device. in order to enter the cfi query mode, the system must write a three-byte sequence, using the cfi query command, to address bkx555h in the last byte sequence. the system can also use the one-byte sequence with address bkx55h and data bus 98h to enter this mode. see figure 18 for cfi entry and read timing diagram. once the device enters the cfi query mode, the system can read cfi data at the addresses given in tables 7 through 9. the system must write the cfi exit command to return to read mode from the cfi query mode. security id the sst36vf160xg offer a 136-word security id space. the secure id space is divided into two segments ? one 128-bit, factory-programmed, segment and one 256-byte, user programmed segment. the first segment is pro- grammed and locked at sst and contains a 128 bit unique id which uniquely identifies the device. the user segment is left un-programmed for the customer to program as desired. the user segment of the security id can be programmed using the security id program command. end-of-write sta- tus is checked by reading th e toggle bits. data# polling is not used for security id end-of-write detection. once the programming is complete, lock the sec id by issuing the user sec id program lock-out command. locking the sec id disables any corruption of this space. note that regardless of whether or not the sec id is locked, the sec id segments can not be erased. the secure id space can be queried by executing a three- byte command sequence with query sec id command (88h) at address 555h in the last byte sequence. see fig- ure 20 for timing diagram. to exit this mode, the exit sec id command should be executed. refer to table 6 for more details.
6 data sheet 16 mbit concurrent superflash sst36vf1601g / sst36vf1602g ?2009 silicon storage technology, inc. s71342-01-000 11/09 product identification the product identification mode identifies the devices as sst36vf1601g or sst36vf1602g and the manufac- turer as sst. for details, see table 3 for software opera- tion, figure 17 for the software id entry and read timing diagram, and figure 27 for the software id entry com- mand sequence flowchart. the addresses a 19 and a 18 indicate a bank address. when the addressed bank is switched to product identification mode, it is possible to read another address from the same bank without issuing a new software id entry command. note: bk = bank address (a 19 -a 18 ) product identification mode exit/cfi mode exit in order to return to the standard read mode, the software product identification mode must be exited. the exit is accomplished by issuing the software id exit command sequence, which returns the device to the read mode. this command may also be used to reset the device to the read mode after any inadvertent transient condition that causes the device to behave abnormally. please note that the software id exit/cfi exit command is ignored during an internal program or erase operation. see table 6 for the software command code, figure 19 for timing waveform and figure 28 for a flowchart. figure 1: functional block diagram table 3: product identification address data manufacturer?s id bk0000h 00bfh device id sst36vf1601g bk0001h 7343h sst36vf1602g bk0001h 7344h t3.0 1342 1342 b01.0 superflash memory 12 mbit bank i/o buffers superflash memory 4 mbit bank memory address dq 15 /a -1 - dq 0 ce# wp# we# oe# control logic rst# byte# ry/by# address buffers (8 kword sector protection)
data sheet 16 mbit concurrent superflash sst36vf1601g / sst36vf1602g 7 ?2009 silicon storage technology, inc. s71342-01-000 11/09 figure 2: sst36vf1601g, 1m x16 concurrent superflash dual-bank memory organization fffffh f8000h block 31 f7fffh f0000h block 30 effffh e8000h block 29 e7fffh e0000h block 28 dffffh d8000h block 27 d7fffh d0000h block 26 cffffh c8000h block 25 c7fffh c0000h block 24 bank 2 bffffh b8000h block 23 b7fffh b0000h block 22 affffh a8000h block 21 a7fffh a0000h block 20 9ffffh 98000h block 19 97fffh 90000h block 18 8ffffh 88000h block 17 87fffh 80000h block 16 7ffffh 78000h block 15 77fffh 70000h block 14 6ffffh 68000h block 13 67fffh 60000h block 12 5ffffh 58000h block 11 57fffh 50000h block 10 4ffffh 48000h block 9 47fffh 40000h block 8 3ffffh 38000h block 7 37fffh 30000h block 6 2ffffh 28000h block 5 27fffh 20000h block 4 1ffffh 18000h block 3 17fffh 10000h block 2 0ffffh 08000h block 1 07fffh 02000h 01fffh 00000h block 0 bank 1 bottom sector protection; 32 kword blocks; 2 kword sectors 8 kword sector protection (4-2 kword sectors) 1342 f01.0 note: the address input range in x16 mode (byte#=v ih ) is a 19 -a 0
8 data sheet 16 mbit concurrent superflash sst36vf1601g / sst36vf1602g ?2009 silicon storage technology, inc. s71342-01-000 11/09 figure 3: sst36vf1601g, 2m x8 concurrent superflash dual-bank memory organization 1fffffh 1f0000h block 31 1effffh 1e0000h block 30 1dffffh 1d0000h block 29 1cffffh 1c0000h block 28 1bffffh 1b0000h block 27 1affffh 1a0000h block 26 19ffffh 190000h block 25 18ffffh 180000h block 24 bank 2 17ffffh 170000h block 23 16ffffh 160000h block 22 15ffffh 150000h block 21 14ffffh 140000h block 20 13ffffh 130000h block 19 12ffffh 120000h block 18 11ffffh 110000h block 17 10ffffh 100000h block 16 0fffffh 0f0000h block 15 0effffh 0e0000h block 14 0dffffh 0d0000h block 13 0cffffh 0c0000h block 12 0bffffh 0b0000h block 11 0affffh 0a0000h block 10 09ffffh 090000h block 9 08ffffh 080000h block 8 07ffffh 070000h block 7 06ffffh 060000h block 6 05ffffh 050000h block 5 04ffffh 040000h block 4 03ffffh 030000h block 3 02ffffh 020000h block 2 01ffffh 010000h block 1 00ffffh 004000h 003fffh 000000h block 0 bank 1 bottom sector protection; 64 kbyte blocks; 4 kbyte sectors 16 kbyte sector protection (4-4 kbyte sectors) 1342 f02.0 note: the address input range in x8 mode (byte#=v il ) is a 19 -a -1
data sheet 16 mbit concurrent superflash sst36vf1601g / sst36vf1602g 9 ?2009 silicon storage technology, inc. s71342-01-000 11/09 figure 4: sst36vf1602g, 1m x16 concurrent superflash dual-bank memory organization top block protection; 32 kword blocks; 2 kword sectors fffffh fe000h fdfffh f8000h block 31 f7fffh f0000h block 30 effffh e8000h block 29 e7fffh e0000h block 28 dffffh d8000h block 27 d7fffh d0000h block 26 cffffh c8000h block 25 c7fffh c0000h block 24 bffffh b8000h block 23 b7fffh b0000h block 22 affffh a8000h block 21 a7fffh a0000h block 20 9ffffh 98000h block 19 97fffh 90000h block 18 8ffffh 88000h block 17 87fffh 80000h block 16 7ffffh 78000h block 15 77fffh 70000h block 14 6ffffh 68000h block 13 67fffh 60000h block 12 5ffffh 58000h block 11 57fffh 50000h block 10 4ffffh 48000h block 9 47fffh 40000h block 8 bank 2 3ffffh 38000h block 7 37fffh 30000h block 6 2ffffh 28000h block 5 27fffh 20000h block 4 1ffffh 18000h block 3 17fffh 10000h block 2 0ffffh 08000h block 1 07fffh 00000h block 0 bank 1 8 kword block protection (4 - 2 kword sectors) 1342 f03.0 note: the address input range in x16 mode (byte#=v ih ) is
10 data sheet 16 mbit concurrent superflash sst36vf1601g / sst36vf1602g ?2009 silicon storage technology, inc. s71342-01-000 11/09 figure 5: sst36vf1602g, 2m x8 concurrent superflash dual-bank memory organization top block protection; 64 kbyte blocks; 4 kbyte sectors block 31 block 30 block 29 block 28 block 27 block 26 block 25 block 24 block 23 block 22 block 21 block 20 block 19 block 18 block 17 block 16 block 15 block 14 block 13 block 12 block 11 block 10 block 9 block 8 bank 2 block 7 block 6 block 5 block 4 block 3 block 2 block 1 block 0 bank 1 16 kbyte block protection (4 - 4 kbyte sectors) 1342 f04.0 1fbfffh 1f0000h 1fffffh 1fc000h 1effffh 1e0000h 1dffffh 1d0000h 1cffffh 1c0000h 1bffffh 1b0000h 1affffh 1a0000h 19ffffh 190000h 18ffffh 180000h 17ffffh 170000h 16ffffh 160000h 15ffffh 150000h 14ffffh 140000h 13ffffh 130000h 12ffffh 120000h 11ffffh 110000h 10ffffh 100000h 0fffffh 0f0000h 0effffh 0e0000h 0dffffh 0d0000h 0cffffh 0c0000h 0bffffh 0b0000h 0affffh 0a0000h 09ffffh 090000h 08ffffh 080000h 07ffffh 070000h 06ffffh 060000h 05ffffh 050000h 04ffffh 040000h 03ffffh 030000h 02ffffh 020000h 01ffffh 010000h 00ffffh 000000h note: the address input range in x8 mode (byte#=v il ) is a 19 -a -1
data sheet 16 mbit concurrent superflash sst36vf1601g / sst36vf1602g 11 ?2009 silicon storage technology, inc. s71342-01-000 11/09 figure 6: pin assignments for 48-ball tfbga (6mm x 8mm) figure 7: pin assignments for 48-lead tsop (12mm x 20mm) a13 a9 we# ry/by# a7 a3 a12 a8 rst# wp# a17 a4 a14 a10 nc a18 a6 a2 a15 a11 a19 nc a5 a1 a16 dq7 dq5 dq2 dq0 a0 byte# dq14 dq12 dq10 dq8 ce# note* dq13 v dd dq11 dq9 oe# v ss dq6 dq4 dq3 dq1 v ss 1342 48-tfbga p1.0 top view (balls facing down) 6 5 4 3 2 1 a b c d e f g h note* = dq 15 /a -1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1342 48-tsop p02.0 standard pinout top view die up a15 a14 a13 a12 a11 a10 a9 a8 a19 nc we# rst# nc wp# ry/by# a18 a17 a7 a6 a5 a4 a3 a2 a1 a16 byte# v ss dq15/a -1 dq7 dq14 dq6 dq13 dq5 dq12 dq4 v dd dq11 dq3 dq10 dq2 dq9 dq1 dq8 dq0 oe# v ss ce# a0
12 data sheet 16 mbit concurrent superflash sst36vf1601g / sst36vf1602g ?2009 silicon storage technology, inc. s71342-01-000 11/09 figure 8: pin assignments for 56-lead lfbga (8mm x 10mm) table 4: pin description symbol name functions a 19 -a 0 address inputs to provide memory addresses. during sector-erase and hardware sector protection, a 19 -a 11 address lines will select the sector. during block-erase a 19 -a 15 address lines will select the block. dq 14 -dq 0 data input/output to output data during read cycles and receive input data during write cycles data is internally latched during a write cycle. the outputs are in tri-state when oe# or ce# is high. dq 15 /a -1 data input/output and lbs address dq 15 is used as data i/o pin when in x16 mode (byte# = ?1?) a -1 is used as the lsb address pin when in x8 mode (byte# = ?0?) ce# chip enable to activate the device when ce# is low. oe# output enable to gate the data output buffers we# write enable to control the write operations rst# hardware reset to reset and return the device to read mode ry/by# ready/busy# to output the status of a program or erase operation ry/by# is a open drain output, so a 10k - 100k pull-up resistor is required to allow ry/by# to transition high indicating the device is ready to read. wp# write protect to protect and unprotect top or bo ttom 8 kword (4 outermost sectors) from erase or program operation. byte# word/byte configuration to select 8-bit or 16-bit mode. v dd power supply to provide 2.7-3.6v power supply voltage v ss ground nc no connection unconnected pins t4.0 1342 1342 56-lfbga p1.0 a11 a8 we# wp# nc a7 a15 a12 a19 nc rst# nc a6 a3 nc a13 a9 nc ry/by# a18 a5 a2 nc a14 a10 a17 a4 a1 a16 nc dq6 dq1 v ss a0 byte# dq15/a -1 dq13 dq4 dq3 dq9 oe# ce# v ss dq7 dq12 nc v dd dq10 dq0 nc dq14 dq5 nc dq11 dq2 dq8 a b c d e f g h 8 7 6 5 4 3 2 1 top view (balls facing down)
data sheet 16 mbit concurrent superflash sst36vf1601g / sst36vf1602g 13 ?2009 silicon storage technology, inc. s71342-01-000 11/09 table 5: operation modes selection mode 1 ce# oe# we# dq 7 -dq 0 dq 15 -dq 8 address byte# = v ih byte# = v il read v il v il v ih d out d out dq 14 -dq 8 = high z a in program v il v ih v il d in d in dq 15 = a -1 a in erase v il v ih v il x 2 x high z sector or block address, 555h for chip-erase standby v ihc x x high z high z high z x write inhibit x v il x high z / d out high z / d out high z x xxv ih high z / d out high z / d out high z x product identification software mode v il v il v ih manufacturer?s id (bfh) manufacturer?s id (00h) high z see table 6 device id 3 device id 3 high z t5.2 1342 1. rst# = v ih for all described operation modes 2. x can be v il or v ih , but no other value. 3. device id = sst36vf1601g = 7343h, sst36vf1602g = 7344h
14 data sheet 16 mbit concurrent superflash sst36vf1601g / sst36vf1602g ?2009 silicon storage technology, inc. s71342-01-000 11/09 table 6: software command sequence command sequence 1st bus write cycle 2nd bus write cycle 3rd bus write cycle 4th bus write cycle 5th bus write cycle 6th bus write cycle addr 1 data 2 addr 1 data 2 addr 1 data 2 addr 1 data 2 addr 1 data 2 addr 1 data 2 program 555h aah 2aah 55h 555h a0h wa 3 data sector-erase 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h sa x 4 50h block-erase 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h ba x 4 30h chip-erase 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h 555h 10h erase-suspend xxxxh b0h erase-resume xxxxh 30h query sec id 5 555h aah 2aah 55h 555h 88h user security id program 555h aah 2aah 55h 555h a5h siwa 6 data user security id program lock-out 7 555h aah 2aah 55h 555h 85h xxh 0000h software id entry 8 555h aah 2aah 55h bk x 9 555h 90h cfi query entry 555h aah 2aah 55h bk x 9 555h 98h cfi query entry bk x 9 55h 98h software id exit/ cfi exit/ sec id exit 10,11 555h aah 2aah 55h 555h f0h software id exit/ cfi exit/ sec id exit 10,11 xxh f0h t6.0 1342 1. address format a 10 -a 0 (hex), addresses a 19 -a 11 can be v il or v ih , but no other value, for the command sequence when in x16 mode. when in x8 mode, addresses a 19 -a 12, address a -1 and dq 14 -dq 8 can be v il or v ih , but no other value, for the command sequence. 2. dq 15 -dq 8 can be v il or v ih , but no other value, for the command sequence 3. wa = program word/byte address 4. sa x for sector-erase; uses a 19 -a 11 address lines ba x for block-erase; uses a 19 -a 15 address lines 5. for sst36vf1601g, sst id is read with a 3 = 0 (address range = 00000h to 00007h), user id is read with a 3 = 1 (address range = = 00008h to 00087h). lock status is read with a 7 -a 0 = 000ffh. unlocked: dq 3 = 1 / locked: dq 3 = 0. for sst36vf1602g, sst id is read with a 3 = 0 (address range = c0000h to c0007h), user id is read with a 3 = 1 (address range = = c0008h to c0087h). lock status is read with a 7 -a 0 = c00ffh. unlocked: dq 3 = 1 / locked: dq 3 = 0. 6. siwa = user security id program word/byte address for sst36vf1601g, valid word-addresses for us er sec id are from 00008h to 00087h. for sst36vf1602g, valid word-addresses for us er sec id are from c0008h to c0087h. all 4 cycles of user security id program and program lock- out must be completed before going back to read-array mode. 7. the user security id program lock-out command must be executed in x16 mode (byte#=v ih ). 8. the device does not remain in software product identification mode if powered down. 9. a 19 and a 18 = bk x (bank address): address of the bank that is switched to software id/cfi mode with a 17 -a 1 = 0;sst manufacturer?s id = 00bfh, is read with a 0 = 0 sst36vf1601g device id = 7343h, is read with a0 = 1 sst36vf1602g device id = 7344h, is read with a0 = 1 10. both software id exit operations are equivalent 11. if users never lock after programming, user sec id can be pr ogrammed over the previously unpr ogrammed bits (data=1) using th e user sec id mode again (the programmed ?0? bits cannot be reversed to ?1?). for sst36vf1601g, valid word-addresses for us er sec id are from 00008h to 00087h. for sst36vf1602g, valid word-addresses for us er sec id are from c0008h to c0087h.
data sheet 16 mbit concurrent superflash sst36vf1601g / sst36vf1602g 15 ?2009 silicon storage technology, inc. s71342-01-000 11/09 table 7: cfi query identification string 1 1. refer to cfi publication 100 for more details. address x16 mode address x8 mode data 2 2. in x8 mode, only the lower byte of data is output. description 10h 20h 0051h query unique ascii string ?qry? 11h 22h 0052h 12h 24h 0059h 13h 26h 0002h primary oem command set 14h 28h 0000h 15h 2ah 0000h address for primary extended table 16h 2ch 0000h 17h 2eh 0000h alternate oem command set (00h = none exists) 18h 30h 0000h 19h 32h 0000h address for alternate oem extended table (00h = none exits) 1ah 34h 0000h t7.0 1342 table 8: system interface information address x16 mode address x8 mode data 1 1. in x8 mode, only the lower byte of data is output. description 1bh 36h 0027h v dd min (program/erase) dq 7 -dq 4 : volts, dq 3 -dq 0 : 100 millivolts 1ch 38h 0036h v dd max (program/erase) dq 7 -dq 4 : volts, dq 3 -dq 0 : 100 millivolts 1dh 3ah 0000h v pp min (00h = no v pp pin) 1eh 3ch 0000h v pp max (00h = no v pp pin) 1fh 3eh 0004h typical time out for program 2 n s (2 4 = 16 s) 20h 40h 0000h typical time out for min size buffer program 2 n s (00h = not supported) 21h 42h 0004h typical time out for individual sector/block-erase 2 n ms (2 4 = 16 ms) 22h 44h 0006h typical time out for chip-erase 2 n ms (2 6 = 64 ms) 23h 46h 0001h maximum time out for program 2 n times typical (2 1 x 2 4 = 32 s) 24h 48h 0000h maximum time out for buffer program 2 n times typical 25h 4ah 0001h maximum time out for individual sector-/block-erase 2 n times typical (2 1 x 2 4 = 32 ms) 26h 4ch 0001h maximum time out for chip-erase 2 n times typical (2 1 x 2 6 = 128 ms) t8.0 1342
16 data sheet 16 mbit concurrent superflash sst36vf1601g / sst36vf1602g ?2009 silicon storage technology, inc. s71342-01-000 11/09 table 9: device geometry information address x16 mode address x8 mode data 1 description 27h 4eh 0015h device size = 2 n bytes (15h = 21; 2 21 = 2 mbyte) 28h 50h 0002h flash device interface description; 0002h = x8/x16 asynchronous interface 29h 52h 0000h 2ah 54h 0000h maximum number of bytes in multi-byte write = 2 n (00h = not supported) 2bh 56h 0000h 2ch 58h 0002h number of erase sector /block sizes supported by device 2dh 5ah 00ffh sector information (y + 1 = numb er of sectors; z x 256b = sector size) 2eh 5ch 0001h y = 511 + 1 = 512 sectors (01ffh = 512) 2fh 5eh 0010h 30h 60h 0000h z = 16 x 256 bytes = 4 kbyte/sector (0010h = 16) 31h 62h 001fh block information (y + 1 = number of blocks; z x 256b = block size) 32h 64h 0000h y = 31 + 1 = 32 blocks (001fh = 31) 33h 66h 0000h 34h 68h 0001h z = 256 x 256 bytes = 64 kbyte/block (0100h = 256) t9.1 1342 1. in x8 mode, only the lower byte of data is output.
data sheet 16 mbit concurrent superflash sst36vf1601g / sst36vf1602g 17 ?2009 silicon storage technology, inc. s71342-01-000 11/09 absolute maximum stress ratings (applied conditions greater than t hose listed under ?absolute maximum stress ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these conditions or conditions greater t han those defined in the operational sections of this data sheet is not implied. exposu re to absolute maximum stress rating co nditions may affect device reliability.) temperature under bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55c to +125c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65c to +150c d. c. voltage on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0. 5v to v dd +0.5v transient voltage (<20 ns) on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0v to v dd +2.0v package power dissipation capability (t a = 25c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0w surface mount solder reflow temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260c for 10 seconds output short circuit current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 ma operating range: range ambient temp v dd commercial 0c to +70c 2.7-3.6v industrial -40c to +85c 2.7-3.6v ac conditions of test input rise/fall time . . . . . . . . . . . . . . 5 ns output load . . . . . . . . . . . . . . . . . . . . c l = 30 pf see figures 23 and 24
18 data sheet 16 mbit concurrent superflash sst36vf1601g / sst36vf1602g ?2009 silicon storage technology, inc. s71342-01-000 11/09 table 10: dc operating characteristics v dd = 2.7-3.6v symbol parameter limits test conditions freq min max units i dd 1 active v dd current read 5 mhz 15 ma ce#=v il, we#=oe#=v ih 1 mhz 4 ma program and erase 30 ma ce#=we#=v il , oe#=v ih concurrent read/write 5 mhz 45 ma ce#=v il, oe#=v ih 1 mhz 35 ma i sb standby v dd current 20 a ce#, rst#=v dd 0.3v i alp auto low power v dd current 20 a ce#=0.1v, v dd =v dd max we#=v dd -0.1v address inputs=0.1v or v dd -0.1v i rt reset v dd current 20 a rst#=gnd i li input leakage current 1 a v in =gnd to v dd , v dd =v dd max i liw input leakage current on wp# pin and rst# pin 10 a wp#=gnd to v dd , v dd =v dd max rst#=gnd to v dd , v dd =v dd max i lo output leakage current 1 a v out =gnd to v dd , v dd =v dd max v il input low voltage 0.8 v v dd =v dd min v ilc input low voltage (cmos) 0.3 v v dd =v dd max v ih input high voltage 0.7 v dd v dd +0.3 v v dd =v dd max v ihc input high voltage (cmos) v dd -0.3 v dd +0.3 v v dd =v dd max v ol output low voltage 0.2 v i ol =100 a, v dd =v dd min v oh output high voltage v dd -0.2 v i oh =-100 a, v dd =v dd min t10.1 1342 1. address input = v ilt /v iht, v dd =v dd max (see figure 23) table 11: recommended system power-up timings symbol parameter minimum units t pu-read 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. power-up to read operation 100 s t pu-write 1 power-up to write operation 100 s t11.0 1342 table 12: capacitance (t a = 25c, f=1 mhz, other pins open) parameter description test condition maximum c i/o 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. i/o pin capacitance v i/o = 0v 10 pf c in 1 input capacitance v in = 0v 10 pf t12.0 1342 table 13: reliability characteristics symbol parameter minimum spec ification units test method n end 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. endurance 10,000 cycles jedec standard a117 t dr 1 data retention 100 years jedec standard a103 i lt h 1 latch up 100 + i dd ma jedec standard 78 t13.0 1342
data sheet 16 mbit concurrent superflash sst36vf1601g / sst36vf1602g 19 ?2009 silicon storage technology, inc. s71342-01-000 11/09 ac characteristics table 14: read cycle timing parameters v dd = 2.7-3.6v symbol parameter min max units t rc read cycle time 70 ns t ce chip enable access time 70 ns t aa address access time 70 ns t oe output enable access time 35 ns t clz 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. ce# low to active output 0 ns t olz 1 oe# low to active output 0 ns t chz 1 ce# high to high-z output 16 ns t ohz 1 oe# high to high-z output 16 ns t oh 1 output hold from address change 0 ns t rp 1 rst# pulse width 500 ns t rhr 1 rst# high before read 50 ns t ry 1,2 2. this parameter applies to sector-erase, block-erase, and program operations. this parameter does not apply to chip-erase operations. rst# pin low to read mode 20 s t14.1 1342 table 15: program/erase cycle timing parameters symbol parameter min max units t bp program time 10 s t as address setup time 0 ns t ah address hold time 40 ns t cs we# and ce# setup time 0 ns t ch we# and ce# hold time 0 ns t oes oe# high setup time 0 ns t oeh oe# high hold time 10 ns t cp ce# pulse width 40 ns t wp we# pulse width 40 ns t wph 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. we# pulse width high 30 ns t cph 1 ce# pulse width high 30 ns t ds data setup time 30 ns t dh 1 data hold time 0 ns t ida 1 software id access and exit time 150 ns t se sector-erase 25 ms t be block-erase 25 ms t sce chip-erase 50 ms t es erase-suspend latency 10 s t by 1,2 2. this parameter applies to sector-erase, block-erase, and program operations. this parameter does not apply to chip-erase operations. ry/by# delay time 90 ns t br 1 bus recovery time 0 s t15.1 1342
20 data sheet 16 mbit concurrent superflash sst36vf1601g / sst36vf1602g ?2009 silicon storage technology, inc. s71342-01-000 11/09 figure 9: read cycle timing diagram figure 10: we# controlled program cycle timing diagram 1342 f05.0 addresses dq 15-0 we# oe# ce# v ih high-z high-z data valid data valid t rc t aa t ce t oe t olz t clz t oh t chz t ohz 1342 f06.0 addresses dq 15-0 ce# 555 2aa 555 addr xxaa xx55 xxa0 data word (addr/data) oe# we# ry/by# valid t dh t wph t as t ch t cs t ah t wp t ds t by t br t bp note: x can be v il or v ih , but no other value.
data sheet 16 mbit concurrent superflash sst36vf1601g / sst36vf1602g 21 ?2009 silicon storage technology, inc. s71342-01-000 11/09 figure 11: ce# controlled program cycle timing diagram figure 12: data# polling timing diagram 1342 f07.1 addresses dq 15-0 ce# 555 2aa 555 addr xxaa xx55 xxa0 data word (addr/data) oe# we# ry/by# valid t dh t cph t as t ch t cs t ah t cp t ds t by t br t bp note: x can be v il or v ih , but no other value. 1342 f08.1 address a 19-0 dq 7 data we# oe# ce# ry/by# data# data# data t oes t oeh t by t ce t oe
22 data sheet 16 mbit concurrent superflash sst36vf1601g / sst36vf1602g ?2009 silicon storage technology, inc. s71342-01-000 11/09 figure 13: toggle bit timing diagram figure 14: we# controlled chip-erase timing diagram 1342 f09.1 address a 19-0 dq 7 we# oe# ce# valid data t oes t oeh t ce t oe two read cycles with same outputs t br 1342 f10.1 addresses dq 15-0 we# 555 2aa 2aa 555 555 xx55 xx10 xx55 xxaa xx80 xxaa 555 oe# ce# ry/by# valid six-byte code for chip-erase t oeh t sce t by t br note: this device also supports ce# c ontrolled block-erase operation. the we# and ce# signals are interchangeable as long as minimum timings are met. see table 15 on page 19. x can be vl or vih, but not other value.
data sheet 16 mbit concurrent superflash sst36vf1601g / sst36vf1602g 23 ?2009 silicon storage technology, inc. s71342-01-000 11/09 figure 15: we# controlled block-erase timing diagram figure 16: we# controlled sector-erase timing diagram 1342 f11.1 addresses dq 15-0 we# 555 2aa 2aa 555 555 xx55 xx50 xx55 xxaa xx80 xxaa ba x oe# ce# ry/by# valid six-byte code for chip-erase t wp t be t by t br note: this device also supports ce# cont rolled block-erase operation. the we# and ce# signals are interchangeable as long as minimum timings are met. see table 15 on page 19. bax = block address x can be vl or vih, but not other value. 1342 f12.1 addresses dq 15-0 we# 555 2aa 2aa 555 555 xx55 xx30 xx55 xxaa xx80 xxaa sa x oe# ce# ry/by# valid six-byte code for chip-erase t wp t se t by t br note: this device also supports cd# controlled secto r-erase operation. the we# and ce# signals are inter- changeable as long as minimum timings are met. see table 15 on page 19. bax = block address x can be vl or vih, but no other value.
24 data sheet 16 mbit concurrent superflash sst36vf1601g / sst36vf1602g ?2009 silicon storage technology, inc. s71342-01-000 11/09 figure 17: software id entry and read figure 18: cfi entry and read 1342 f13.1 addresses dq 15-0 we# 555 2aa 555 0000 0001 oe# ce# 00bf device id xx55 xxaa xx90 three-byte sequence for software id entry t wph t ida t wp t aa note: device id = 7343h for sst36vf1601g, and 7344h for sst36vf1602g x can be v il or v ih , but no other value. 1342 f14.1 addresses dq 15-0 we# 555 2aa 555 oe# ce# xx55 xxaa xx98 three-byte sequence for cfi query entry t wph t ida t wp t aa note: x can be v il or v ih , but no other value.
data sheet 16 mbit concurrent superflash sst36vf1601g / sst36vf1602g 25 ?2009 silicon storage technology, inc. s71342-01-000 11/09 figure 19: software id exit/cfi exit figure 20: sec id entry 1342 f15.1 addresses dq 15-0 we# 555 2aa 555 oe# ce# xx55 xxaa xxf0 three-byte sequence for software id exit and reset t wph t ida t wp note: x can be v il or v ih , but no other value. 1342 f16.1 addresses dq 15-0 we# 555 2aa 555 oe# ce# xx55 xxaa xx88 sw0 sw2 sw1 three-byte sequence for cfi query entry t wph t ida t wp t aa note: wp# must be held in proper logic state (v il or v ih ) 1s prior to and 1 s after the command sequence. x can be v il or v ih , but no other value.
26 data sheet 16 mbit concurrent superflash sst36vf1601g / sst36vf1602g ?2009 silicon storage technology, inc. s71342-01-000 11/09 figure 21: rst# timing diagram (when no internal operation is in progress) figure 22: rst# timing diagram (during sector- or block-erase operation) 1342 f17.0 ry/by# 0v rst# ce#/oe# t rp t rhr 1342 f18.0 ry/by# ce# oe# t rp t ry t br rst#
data sheet 16 mbit concurrent superflash sst36vf1601g / sst36vf1602g 27 ?2009 silicon storage technology, inc. s71342-01-000 11/09 figure 23: ac input/output reference waveforms figure 24: a test load example 1342 f19.0 reference points output input v it v iht v ilt v ot ac test inputs are driven at v iht (0.9 v dd ) for a logic ?1? and v ilt (0.1 v dd ) for a logic ?0?. measurement reference points for inputs and outputs are v it (0.5 v dd ) and v ot (0.5 v dd ). input rise and fall times (10% ? 90%) are <5 ns. note: v it - v input te s t v ot - v output te s t v iht - v input high test v ilt - v input low test 1342 f20.0 to tester to dut c l
28 data sheet 16 mbit concurrent superflash sst36vf1601g / sst36vf1602g ?2009 silicon storage technology, inc. s71342-01-000 11/09 figure 25: program algorithm 1342 f21.0 start load data: xxaah address: 555h load data: xx55h address: 2aah load data: xxa0h address: 555h load address/data wait for end of program (t bp , data# polling bit, or toggle bit operation) program completed note: x can be v il or v ih , but no other value.
data sheet 16 mbit concurrent superflash sst36vf1601g / sst36vf1602g 29 ?2009 silicon storage technology, inc. s71342-01-000 11/09 figure 26: wait options 1342 f22.0 wait t bp , t sce , t se or t be program/erase initiated internal timer toggle bit ye s ye s no no program/erase completed does dq 6 match? read same byte/word data# polling program/erase completed program/erase completed read byte/word is dq 7 = true data? read dq 7 program/erase initiated program/erase initiated
30 data sheet 16 mbit concurrent superflash sst36vf1601g / sst36vf1602g ?2009 silicon storage technology, inc. s71342-01-000 11/09 figure 27: software product id/cfi/sec id entry command flowcharts 1342 f23.0 load data: xxaah address: 555h software product id entry command sequence load data: xx55h address: 2aah load data: xx90h address: 555h wait t ida read software id load data: xxaah address: 555h cfi query entry command sequence load data: xx55h address: 2aah load data: xx98h address: 555h wait t ida read cfi data load data: xxaah address: 555h sec id query entry command sequence load data: xx55h address: 2aah load data: xx88h address: 555h wait t ida read sec id x can be v il or v ih , but no other value
data sheet 16 mbit concurrent superflash sst36vf1601g / sst36vf1602g 31 ?2009 silicon storage technology, inc. s71342-01-000 11/09 figure 28: software product id/cfi/sec id exit command flowcharts 1342 f24.0 load data: xxaah address: 555h software id exit/cfi exit/sec id exit command sequence load data: xx55h address: 2aah load data: xxf0h address: 555h load data: xxf0h address: xxh return to normal operation wait t ida wait t ida return to normal operation x can be v il or v ih, but no other value
32 data sheet 16 mbit concurrent superflash sst36vf1601g / sst36vf1602g ?2009 silicon storage technology, inc. s71342-01-000 11/09 figure 29: erase command sequence 1342f25.0 load data: xxaah address: 555h chip-erase command sequence load data: xx55h address: 2aah load data: xx80h address: 555h load data: xx55h address: 2aah load data: xx10h address: 555h load data: xxaah address: 555h wait t sce chip erased to ffffh load data: xxaah address: 555h sector-erase command sequence load data: xx55h address: 2aah load data: xx80h address: 555h load data: xx55h address: 2aah load data: xx50h address: sa x load data: xxaah address: 555h wait t se sector erased to ffffh load data: xxaah address: 555h block-erase command sequence load data: xx55h address: 2aah load data: xx80h address: 555h load data: xx55h address: 2aah load data: xx30h address: ba x load data: xxaah address: 555h wait t be block erased to ffffh note: x can be v il or v ih, but no other value.
data sheet 16 mbit concurrent superflash sst36vf1601g / sst36vf1602g 33 ?2009 silicon storage technology, inc. s71342-01-000 11/09 product ordering information valid combinations for sst36vf1601g sst36vf1601g-70-4i-b3ke sst36vf1601g-70-4i-eke sst36vf1601g-70-4i-l1pe valid combinations for sst36vf1602g sst36vf1602g-70-4i-b3ke SST36VF1602G-70-4I-EKE sst36vf1602g-70-4i-l1pe note: valid combinations are those products in mass producti on or will be in mass production. consult your sst sales representative to confirm availability of valid combinat ions and to determine availability of new combinations. environmental attribute e 1 = non-pb package modifier k = 48 balls or leads package type b3 = tfbga (6mm x 8mm) e =tsop (type 1, die up, 12mm x 20mm) l1p = lfbga (8mm x 10mm) temperature range i = industrial = -40c to +85c minimum endurance 4 = 10,000 cycles read access speed 70 = 70 ns bank split 1 = 4 mbit + 12 mbit 2 = 12 mbit + 4 mbit device density 160 = 1 mbit x16 or 2 mbit x8 voltage v = 2.7-3.6v product series 36 = concurrent superflash 1. environmental suffix ?e? denotes non-pb solder. sst non-pb solder devices are ?rohs compliant?. sst 36 vf 1601g - 70 - 4c - b3k e xx x x xxx x x - xxx -xx -xx x x
34 data sheet 16 mbit concurrent superflash sst36vf1601g / sst36vf1602g ?2009 silicon storage technology, inc. s71342-01-000 11/09 packaging diagrams figure 30: 48-ball thin-profile, fine-pitch ball grid array (tfbga) 6mm x 8mm sst package code: b3k a1 corner h g f e d c b a a b c d e f g h bottom view top view side view 6 5 4 3 2 1 6 5 4 3 2 1 seating plane 0.35 0.05 1.10 0.10 0.12 6.00 0.20 0.45 0.05 (48x) a1 corner 8.00 0.20 0.80 4.00 0.80 5.60 48-tfbga-b3k-6x8-450mic-4 note: 1. complies with jedec publication 95, mo-210, variant 'ab-1', although some dimensions may be more stringent. 2. all linear dimensions are in millimeters. 3. coplanarity: 0.12 mm 4. ball opening size is 0.38 mm ( 0.05 mm) 1mm
data sheet 16 mbit concurrent superflash sst36vf1601g / sst36vf1602g 35 ?2009 silicon storage technology, inc. s71342-01-000 11/09 figure 31: 48-lead thin small outline package (tsop) 12mm x 20mm sst package code: ek 1.05 0.95 0.70 0.50 18.50 18.30 20.20 19.80 0.70 0.50 12.20 11.80 0.27 0.17 0.15 0.05 48-tsop-ek-8 note: 1. complies with jedec publication 95 mo-142 dd dimensions, although some dimensions may be more stringent. 2. all linear dimensions are in millimeters (max/min). 3. coplanarity: 0.1 mm 4. maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads. 1.20 max. 1mm 0- 5 detail pin # 1 identifier 0. 50 bsc
36 data sheet 16 mbit concurrent superflash sst36vf1601g / sst36vf1602g ?2009 silicon storage technology, inc. s71342-01-000 11/09 figure 32: 56-ball, low-profile, fine-pitch ball grid array (lfbga) 8mm x 10mm sst package code: l1p table 16: revision history number description date 00 ? initial release of data sheet dec 2006 01 ? edited tby ty/by# delay time in table 15 on page 19 from 90ns min to 90ns max nov 2009 h g f e d c b a a b c d e f g h side view 8 7 6 5 4 3 2 1 seating plane 0.35 0.05 1.30 0.10 0.12 0.45 0.05 (56x) 0.80 5.60 0.80 5.60 56-lfbga-l1p-8x10-450mic-4 note: 1. although many dimensions are similar to those of jedec publication 95, mo-210, this specific package is not registere d. 2. all linear dimensions are in millimeters. 3. coplanarity: 0.12 mm 4. ball opening size is 0.38 mm ( 0.05 mm) 8 7 6 5 4 3 2 1 1mm a1 corner bottom view top view 8.00 0.20 a1 corner 10.00 0.20 silicon storage technology, inc. ? 1171 sonora court ? sunnyvale, ca 94086 ? telephone 408-735-9110 ? fax 408-735-9036 www.superflash.com or www.sst.com

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